In the design of dynamic random access memories (DRAMs), there is a drive to increase integration by reducing the surface area of the substrate occupied by each memory cell. Accordingly, there is a drive to reduce the size of the capacitor used in each memory cell. A reduction in size of the capacitor, however, may reduce the read/write capability of each memory cell and also increase the soft error rate. In addition, a smaller capacitor makes it difficult to operate a DRAM at a low voltage thus increasing the power consumed by the memory. Thus, there is a need in the art to reduce the size of capacitors in memory cells without significantly reducing the capacitance.
One approach to this problem has been to increase the electrostatic capacity of a capacitor per unit surface area of a substrate occupied. For example, there has been proposed a capacitor having a cylindrical structure in which inner and outer regions of the cylindrical structure are used to increase the surface area of an electrode (or plate) of the capacitor so that the capacitance can be increased.
In particular, Korean Patent Application No. 91-15250 discusses a method for fabricating a capacitor having a cylindrical structure. This method is described with reference to FIGS. 1A-1G.
In FIG. 1A, the semiconductor substrate 1 includes at least one transistor. An insulating layer 3 is formed on the semiconductor substrate 1, and a photoresist pattern PR1 is formed on the insulating layer 3 using a photolithographic process.
In FIG. 1B, a contact hole is formed in the insulating layer 3, and this contact hole provides contact with a storage node. The insulating layer 3 may be dry-etched by using the photoresist pattern PR1 to form a contact hole. The resist pattern PR1 can then be removed and a polysilicon layer 5 can be deposited.
The step of forming an etching mask for a cylindrical node pattern is illustrated in FIGS. 1C and 1D. As shown in FIG. 1C, a photoresist pattern PR2 and an oxide layer 6 are formed on the polysilicon layer 5. The oxide layer 6 is then anisotropically etched to form spacers 6a on both sidewalls of the resist pattern PR2. As shown in FIG. 1E, an outer surface of a cylinder is formed by etching portions of the polysilicon layer 5 which are not covered by the resist pattern PR2 or the oxide spacer 6a. The thickness of the resist pattern PR2 may also be reduced during this etching step.
The step of forming an inner surface of the cylinder is illustrated in FIG. 1F. The remaining portion of the resist pattern PR2 is removed and then the exposed portion of the polysilicon layer 5 is further etched by a dry-etching method, thereby forming the cylindrical storage electrode 5a. The spacers 6a are then removed as illustrated in FIG. 1G. A thin dielectric layer 7 is formed on the surface of the cylindrical storage electrode 5a, and a polysilicon layer 9 is formed on the surface of the resulting structure. A second polysilicon layer 9 forms a top electrode (or plate electrode) of the cylindrical capacitor structure.
In the method discussed above, however, it may be difficult to reproducibly form the spacers 6a which determine the pattern of the first capacitor electrode 5a. This difficulty may result because the photoresist layer PR2 may be deformed during the deposition of the material used to form the spacers 6a. For example, portions of the photoresist may be deformed or destroyed as a result of a high temperature deposition. In addition, it may be difficult to form a capacitor electrode 5a having the desired width and uniformity. This difficulty may result because the width of the spacer 6a is determined by the resolution of the photolithography process used, and because when the oxide layer 6 is anisotropically etched, the etch rate may not be uniform across the substrate.